Verilog RISC Processor

• Category: Coursework
• Class: CPEN 211 (Tor Aamodt)
• Project date: December, 2021
• Project URL: N/A

Utilized ModelSim and Quartus to develop a RISC Processor to gain a further understanding of the ARM ISA. Powered by a finite state machine, the processor supports most of the arm instructions including branching and function calls with support of memory-mapped I/O.